Design trade-off in merged DRAM logic for video signal processing

نویسندگان

  • Sunho Chang
  • Lee-Sup Kim
چکیده

The trade-off in designing merged DRAM logic (MDL) is explored for video signal processing. Computing requirements and memory bandwidths are quantitatively analyzed in the programmable MDL architecture. The number of processing elements (NPE) and the number of bus width (NBW) are obtained as a function of macro block rate, clock frequency, data rate, and number of clock/memory access cycles. Optimal MDL design parameters are determined from the minimum cost and design metrics: DRAM access rate (DAR) and area ratio of DRAM (ARD).

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A programmable 3.2-GOPS merged DRAM logic for video signal processing

This paper proposes a programmable high-performance architecture of datapath in the merged DRAM logic (MDL) for video signal processing. A model of a datapath in the programmable MDL is generated, and two basic parameters, total required clock cycles (TRCC) and DRAM access rate (DAR), are defined by analysis of the model. Design guidelines are suggested for the optimized video signal processor ...

متن کامل

Assessing Merged DRAM Logic Technology Submitted to Integration the VLSI Journal

This paper describes the impact of DRAM process on the logic circuit performance of Memory Logic Merged Integrated Circuit and the alternative circuit design technology to o set the performance penalty Extensive circuit and routing simulations have been performed to study the logic circuit performance degradation when the merged chip is implemented on DRAM process Three logic processes m m and ...

متن کامل

Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead

This paper describes a novel memory hierarchy and line-pixel-lookahead (LPL) for an H.264/AVC video decoder. The memory system is the bottleneck of most video processors, particularly in the newly announced H.264/AVC. This is because it utilizes the neighboring pixels to create a reliable predictor, leading to a dependency on a long past history of data. This problem can be resolved by allocati...

متن کامل

Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs

This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called “dynamically variable line-size cache (D-VLS cache).” The D-VLS cache can optimize its line-size according to the characteristic of programs, and attempts to improve the performance by exploiting the high on-chip memory bandwidth on merged DRAM/logic LSIs appropriately. In our evaluation, it is o...

متن کامل

Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems

Integrating main memory (DRAM) and processors into a single chip, or merged DRAM/logic LSI, makes it possible to exploit high on-chip memory bandwidth by widening on-chip bus and on-chip DRAM array. In addition, from energy consumption point of view, the integration brings a significant improvement by decreasing the number of off-chip accesses. For merged DRAM/logic LSIs having on-chip cache me...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2001